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KM416S1021C
512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface
FEATURES
* JEDEC standard 3.3V power supply * SSTL_3 (Class II) compatible with multiplexed address * Dual banks operation * MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Burst type (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock. * Burst read single-bit write operation * DQM for masking * Auto & self refresh * 64ms refresh period (4K cycle)
Preliminary CMOS SDRAM
GENERAL DESCRIPTION
The KM416S1021C is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part No. KM416S1021CT-G7 KM416S1021CT-GS Max Freq. 143MHz 100MHz(CL=2) Interface Package SSTL_3 (Class II) 54 TSOP(II)
KM416S1021CT-G8 125MHz * KM416S1021CT-GS : CL=2 only
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select Refresh Counter
Output Buffer
Row Decoder
Sense AMP
512K x 16
Row Buffer
DQi
Address Register
CLK ADD
512K x 16
Column Decoder Col. Buffer Latency & Burst Length
LRAS
LCBR
LCKE LRAS LCBR LWE LCAS
Programming Register LWCBR LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM * Samsung Electronics reserves the right to change products or specification without notice.
REV. 1. May '98
KM416S1021C
PIN CONFIGURATION (Top view)
VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ VREF UDQM CLK CKE N.C A9 A8 A7 A6 A5 A4 VSS
Preliminary CMOS SDRAM
50Pin TSOP (II) (400mil x 825mil) (0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, Column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide improved noise immunity. Reference voltage for inputs.
CKE
Clock enable
A0 ~ A10/AP BA RAS CAS WE L(U)DQM DQ0 ~ 15 VDD/VSS VDDQ/VSSQ VREF
Address Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground Data output power/ground Reference voltage
REV. 1. May '98
KM416S1021C
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1 50
Preliminary CMOS SDRAM
Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Device supply voltage Output supply voltage Input reference voltage Termination voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Output leakage current Symbol VDD VDDQ VREF Vtt VIH VIL VOH VOL IIL IOL Min VDDQ 3.0 3.26 1.3 VREF-0.05 VREF+0.2 -0.3 Vtt+0.8 -5 -5 Typ 3.3 3.43 1.5 VREF 0 Max 3.6 3.6 3.6 1.7 VREF+0.05 VDD+0.3 VREF-0.2 Vtt-0.8 5 5 Unit V V V V V V V V V uA uA 1 2 5 5 6 7 Note 1 1 8 2, 3
Notes : 1.Under all conditions, VDDQ must be less than or equal to VDD. 2. Typically, the value of VREF is expected to be about 0.45 * VDDQ of the transmitting device. VREF is expected to track variations in VDDQ. 3. Peak to peak AC noise on VREF may not exceed 2% VREF (DC) 4. Vtt of transmitting device must track VREF of receiving device. 5. Voltage level measured at device pin with IOH/IOL = -16mA/16mA. 6. Any input 0V VIN VDD+0.3V, all other pins are not under test = 0V. 7. Dout buffer is disabled, 0V VOUT VDD. 8. Apply to only the KM416S1021CT-GS.
CAPACITANCE
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200 mV) Symbol CIN CADD COUT Min 2 2 2 Max 4 4 5 Unit pF pF pF
Parameter CLK, CKE, CS, RAS, CAS, WE & L(U)DQM Address DQ0 ~ DQ15
REV. 1. May '98
KM416S1021C
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Symbol Test Condition Burst length = 1 tRC tRC(min) IOL = 0 mA CKE VIL(max), tCC = 15ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 15ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 15ns Input signals are changed one time during 30ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IOL = 0 mA Page burst tCCD = 2CLKs tRC tRC(min) CKE VIL(max) 3 2 150 105 90 CAS Latency
Preliminary CMOS SDRAM
Version -7 95 -S 90 2 2 20 -8 95
Unit
Note
Operating current (One bank active) Precharge standby current in power-down mode
ICC1 ICC2P ICC2PS ICC2N
mA
1
mA
Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode ICC3P ICC3PS ICC3N ICC3NS
mA 6 3 2 30 20 140 100 85 2 130 mA 100 80 mA mA 2 3 1 mA mA
mA
Active Standby current in non power-down mode (One bank active)
Operating current (Burst mode) Refresh current Self refresh current
ICC4 ICC5 ICC6
Notes :1. Measured with outputs open. 2. Refresh period is 64ms.
REV. 1. May '98
KM416S1021C
AC OPERATING TEST CONDITIONS(VDD = 3.3V 0.3V, 3.43V 0.5%, TA = 0 to 70C)
Parameter Input reference voltage Input signal maximum peak swing Inout signal minimum slew rate AC input levels (Vih/Vil) Input timing measurement reference level Output timing measurement reference level Output load condition
Vtt = 0.45 * VDDQ
Preliminary CMOS SDRAM
Value 0.45 * VDDQ 2.0 1.0 VREF+0.4/VREF-0.4 VREF Vtt See Fig. 1 Unit V V V/ns V V V
50 Output Z0 = 50
VREF = 0.45 * VDDQ
CLOAD=30pF
(Fig. 1) Output load circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to new col. address delay Last data in to row precharge Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol -7 tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tCDL(min) tRDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 2 1 70 14 21 21 49 Version -S 20 20 20 50 100 70 1 1 1 1 1 2 1 80 -8 16 24 24 56 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2 2 2 3 4 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
REV. 1. May '98
KM416S1021C
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter CAS latency=3 CAS latency=2 CLK to Valid Output Delay CAS latency=3 CAS latency=2 tOH tCH tCL tSS tSH tSLZ tSHZ 2.5 3 3 2 1 1 5.5 7 tSAC Symbol Min CLK cycle time tCC 7 12 5.5 7 2 3.5 3.5 2 1 1 8 -7 Max 1000 Min 10 6 2.5 3 3 2.5 1 1 -S Max 1000 Min 8 13 -8
Preliminary CMOS SDRAM
Unit Max 1000 6 8 ns ns ns ns ns ns 6 8 ns ns
Note
1
ns
1,2 2 3 3 3 3 2
Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
REV. 1. May '98
KM416S1021C
FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE
KM416S1021BT-G7
Frequency 143MHz (7.0ns) 125MHz (8.0ns) 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) CAS Latency 3 3 3 2 2 2 tRC 70ns 10 9 7 6 6 5 tRAS 49ns 7 7 5 5 4 4 tRP 21ns 3 3 3 2 2 2 tRRD 14ns 2 2 2 2 2 1 tRCD 21ns 3 3 3 2 2 2
Preliminary CMOS SDRAM
(Unit : Number of clock) tCCD 7ns 1 1 1 1 1 1 tCDL 7ns 1 1 1 1 1 1 tRDL 7ns 1 1 1 1 1 1
KM416S1021BT-GS
Frequency 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) CAS Latency 2 2 2 2 2 tRC 70ns 7 6 6 5 5 tRAS 50ns 5 5 4 4 3 tRP 20ns 2 2 2 2 2 tRRD 20ns 2 2 2 2 2 tRCD 20ns 2 2 2 2 2 tCCD 10ns 1 1 1 1 1
(Unit : Number of clock) tCDL 10ns 1 1 1 1 1 tRDL 10ns 1 1 1 1 1
KM416S1021BT-G8
Frequency 125MHz (8.0ns) 100MHz (10.0ns) 83MHz (12.0ns) 75MHz (13.0ns) 66MHz (15.0ns) 60MHz (16.7ns) CAS Latency 3 3 3 2 2 2 tRC 80ns 10 8 7 7 6 5 tRAS 56ns 7 6 5 5 4 4 tRP 24ns 3 3 2 2 2 2 tRRD 16ns 2 2 2 2 2 1 tRCD 24ns 3 3 2 2 2 2 tCCD 8ns 1 1 1 1 1 1
(Unit : Number of clock) tCDL 8ns 1 1 1 1 1 1 tRDL 8ns 1 1 1 1 1 1
REV. 1. May '98
KM416S1021C
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H
CKEn-1 CKEn CS RAS CAS WE DQM BA
Preliminary CMOS SDRAM
A10/AP A9 ~ A0 Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP code X
1,2 3 3
X X X V V
X Row address L H
Column address (A0 ~ A7) Column address (A0 ~ A7)
3 3
Bank active & row addr. Read & column address Write & column address Burst stop Precharge Bank selection Both banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
L L
4 4,5 4 4,5 6
H H H
X X X
L L L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
(V=Valid, X=Dont care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A10/AP, BA : Program keys. (@ MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state. 4. BA : bank select address. If "Low" at read, write, row active and precharge, bank A is selected. If "High" at read, write, row active and precharge, bank B is selected. If A10/AP is "High" at row precharge, BA is ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
REV. 1. May '98

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